Empirical Study of Power Consumption of x86-64 Instruction Decoder

It has been a common myth that x86-64 processors suffer in terms of energy efficiency because of their complex instruction set. In this paper, we aim to investigate whether this myth holds true, and determine the power consumption of the instruction decoders of an x86-64 processor. To that end, we design a set of microbenchmarks that specifically trigger the instruction decoders by exceeding the capacity of the decoded instruction cache. We measure the power consumption of the processor package using a hardware-level energy metering model called the Running Average Power Limit (RAPL), which is supported in the latest Intel architectures. We leverage linear regression modeling to break down the power consumption of each processor component, including the instruction decoders. Through a comprehensive set of experiments, we demonstrate that the instruction decoders can consume between 3% and 10% of the package power when the capacity of the decoded instruction cache is exceeded. Overall, this is a somewhat limited amount of power compared with the other components in the processor core, e.g., the L2 cache. We hope our finding can shed light on the future optimization of processor architectures.